Engineering SatnaOS: 32-Bit x86 Kernel from Bare Metal

Systems Engineering & Low-Level Architecture · 2026

An in-depth systems research paper detailing the design and implementation of a 32-bit multitasking operating system kernel constructed entirely from first principles—progressing from hardware reset vector bootstrapping to protected mode, two-level 4KB paging, round-robin multitasking, and an interactive shell.

1. The Bootstrapping Paradox: Execution Before the OS Exists

In modern application engineering, programmers rely on an implicit safety net: the operating system provides an address space, dynamically links libraries, initializes the stack, and executes main(). When building an operating system, however, **there is no runtime, no virtual memory, and no library support**.

To maintain backward compatibility with the original 1978 Intel 8086 processor, every modern x86 CPU powers on in **16-bit Real Address Mode**. Hardware initialization proceeds through a strict chain of custody:

1. Hardware Reset

CPU registers initialize to fixed states: CS = 0xF000, IP = 0xFFF0. The processor begins execution at physical address 0xFFFF0, jumping into BIOS ROM firmware.

2. POST & Enumerate

The BIOS performs the Power-On Self Test, initializes motherboard chipsets, tests system RAM, and enumerates available boot media (SATA, IDE, USB).

3. Hand-off at 0x7C00

BIOS copies the first 512-byte sector (MBR) into physical memory at address 0x0000:0x7C00, validates the 0xAA55 magic signature, and jumps to it.

2. Physical Memory Topology: The First Megabyte

In 16-bit Real Mode, the processor uses 20-bit addresses ($\text{Segment} \ll 4 + \text{Offset}$), restricting physical access to exactly 1 MB ($2^{20}\text{ bytes}$). The low memory layout dictates where our kernel can safely operate without overwriting hardware dispatch tables or video buffers.

Physical Address Range	Size	Purpose & Architectural Role
`0x00000 - 0x003FF`	1,024 B	Interrupt Vector Table (IVT): 256 far pointers to BIOS/hardware interrupt handlers.
`0x00400 - 0x004FF`	256 B	BIOS Data Area (BDA): Keyboard state, timer ticks, disk parameters.
`0x00500 - 0x07BFF`	~30 KB	Conventional Free Memory: Usable bootloader workspace and stack.
`0x07C00 - 0x07DFF`	512 B	Master Boot Record (MBR): Staging area for `boot.bin`.
`0x07E00 - 0x7FFFF`	~480 KB	Target Kernel Buffer: Destination area for loading multi-sector kernel code.
`0xB8000 - 0xBFFFF`	32 KB	VGA Color Text Buffer: Memory-mapped display buffer (80 × 25 characters).

Real Mode vs. Protected Mode

The architectural gulf between Real Mode and 32-bit Protected Mode is vast. Real Mode is constrained to 1 MB with zero privilege separation. Protected Mode unlocks a 4 GB flat linear address space with two-level 4KB paging and hardware privilege isolation (Ring 0 Kernel vs. Ring 3 User).

3. Step-by-Step Kernel Bringup Pipeline

Explore the engineering phases involved in progressing from a raw 512-byte MBR to a preemptive protected-mode kernel:

Phase 1

Real-Mode MBR Bootloader

Dissection of the 512-byte boot sector.

; Loading code...

4. The C++ Developer's Mental Bridge

For developers coming from an intermediate C++ background, bare-metal engineering can initially feel alien due to the absence of the standard library and runtime guarantees. However, low-level mechanics map cleanly to familiar C++ concepts:

Raw Pointers & Dereferencing

Writing directly to memory-mapped hardware like the VGA buffer at 0xB8000 is identical to reinterpret_cast<uint8_t*>(0xB8000). In assembly, brackets [reg] denote dereferencing.

Virtual Tables vs. The IDT

C++ virtual method tables (vptr/vtbl) are arrays of function pointers indexed by method index. The CPU's Interrupt Descriptor Table (IDT) is literally a hardware vtable indexed by interrupt vector number.

RAII & The Call Stack

C++ stack unwinding relies on the frame pointer (EBP/RBP) and stack pointer (ESP/RSP). Assembly requires manual management via push, pop, call, and ret.

Dynamic Allocation Without Libc

new and delete rely on OS-level brk/mmap allocators. In kernel space, we build the memory allocator (kmalloc/kfree) directly on top of 4KB physical page frames.

5. Interactive Systems Concept Analyzer

Have questions about CPU registers, memory segmentation, or protected mode switching? Enter a systems concept or assembly instruction below for an architectural breakdown:

6. Project Trajectory & Ongoing Milestones

SatnaOS is engineered in 8 rigorous phases. With Phase 2 validated in QEMU, the system is advancing into multi-sector disk storage via BIOS INT 0x13 before initializing the 32-bit Global Descriptor Table.

Full technical logs, instruction decoding tables, and hardware register references are actively maintained in the project's documentation repository.